First Bus for Quantum Computing Designed

RMIT University researchers have trialled a quantum processor capable of routing quantum information from different locations in a critical breakthrough for quantum computing.

The work opens a pathway towards the "quantum data bus", a vital component of future quantum technologies.

The research team from the Quantum Photonics Laboratory at RMIT in Melbourne, Australia, the Institute for Photonics and Nanotechnologies of the CNR in Italy and the South University of Science and Technology of China, have demonstrated for the first time the perfect state transfer of an entangled quantum bit (qubit) on an integrated photonic device.

Quantum Photonics Laboratory Director Dr Alberto Peruzzo said after more than a decade of global research in the specialised area, the RMIT results were highly anticipated.

"The perfect state transfer has emerged as a promising technique for data routing in large-scale quantum computers," Peruzzo said.

link.

Once Again, Moore's Law is Toast

As reported at The Motley Fool, Intel’s latest 10-K / annual report filing would seem to suggest that the ‘Tick-Tock’ strategy of introducing a new lithographic process note in one product cycle (a ‘tick’) and then an upgraded microarchitecture the next product cycle (a ‘tock’) is going to fall by the wayside for the next two lithographic nodes at a minimum, to be replaced with a three element cycle known as ‘Process-Architecture-Optimization’.

Intel’s Tick-Tock strategy has been the bedrock of their microprocessor dominance of the last decade. Throughout the tenure, every other year Intel would upgrade their fabrication plants to be able to produce processors with a smaller feature set, improving die area, power consumption, and slight optimizations of the microarchitecture, and in the years between the upgrades would launch a new set of processors based on a wholly new (sometimes paradigm shifting) microarchitecture for large performance upgrades. However, due to the difficulty of implementing a ‘tick’, the ever decreasing process node size and complexity therein, as reported previously with 14nm and the introduction of Kaby Lake, Intel’s latest filing would suggest that 10nm will follow a similar pattern as 14nm by introducing a third stage to the cadence.

link.

2nd link.

Intel's Annual Report (PDF).

Moore's Law is Dead: Get Over it

Next month, the worldwide semiconductor industry will formally acknowledge what has become increasingly obvious to everyone involved: Moore's law, the principle that has powered the information-technology revolution since the 1960s, is nearing its end.

A rule of thumb that has come to dominate computing, Moore's law states that the number of transistors on a microprocessor chip will double every two years or so — which has generally meant that the chip's performance will, too. The exponential improvement that the law describes transformed the first crude home computers of the 1970s into the sophisticated machines of the 1980s and 1990s, and from there gave rise to high-speed Internet, smartphones and the wired-up cars, refrigerators and thermostats that are becoming prevalent today.

None of this was inevitable: chipmakers deliberately chose to stay on the Moore's law track. At every stage, software developers came up with applications that strained the capabilities of existing chips; consumers asked more of their devices; and manufacturers rushed to meet that demand with next-generation chips. Since the 1990s, in fact, the semiconductor industry has released a research road map every two years to coordinate what its hundreds of manufacturers and suppliers are doing to stay in step with the law — a strategy sometimes called More Moore. It has been largely thanks to this road map that computers have followed the law's exponential demands.

Not for much longer. The doubling has already started to falter, thanks to the heat that is unavoidably generated when more and more silicon circuitry is jammed into the same small area. And some even more fundamental limits loom less than a decade away. Top-of-the-line microprocessors currently have circuit features that are around 14 nanometres across, smaller than most viruses. But by the early 2020s, says Paolo Gargini, chair of the road-mapping organization, “even with super-aggressive efforts, we'll get to the 2–3-nanometre limit, where features are just 10 atoms across. Is that a device at all?” Probably not — if only because at that scale, electron behaviour will be governed by quantum uncertainties that will make transistors hopelessly unreliable. And despite vigorous research efforts, there is no obvious successor to today's silicon technology.

The industry road map released next month will for the first time lay out a research and development plan that is not centred on Moore's law. Instead, it will follow what might be called the More than Moore strategy: rather than making the chips better and letting the applications follow, it will start with applications — from smartphones and supercomputers to data centres in the cloud — and work downwards to see what chips are needed to support them. Among those chips will be new generations of sensors, power-management circuits and other silicon devices required by a world in which computing is increasingly mobile.

link.

Columbia Develops Biologically Powered Computer Chip

Columbia Engineering researchers have, for the first time, harnessed the molecular machinery of living systems to power an integrated circuit from adenosine triphosphate (ATP), the energy currency of life. They achieved this by integrating a conventional solid-state complementary metal-oxide-semiconductor (CMOS) integrated circuit with an artificial lipid bilayer membrane containing ATP-powered ion pumps, opening the door to creating entirely new artificial systems that contain both biological and solid-state components. The study, led by Ken Shepard, Lau Family Professor of Electrical Engineering and professor of biomedical engineering at Columbia Engineering, is published online Dec. 7 in Nature Communications.

link.

Los Alamos, Stanford and Technical University of Munich Identify Techniques for Using Standard Silicon for Quantum Computers

Physicists at the Technical University of Munich, the Los Alamos National Laboratory and Stanford University (USA) have tracked down semiconductor nanostructure mechanisms that can result in the loss of stored information - and halted the amnesia using an external magnetic field. The new nanostructures comprise common semiconductor materials compatible with standard manufacturing processes.

Quantum bits, qubits for short, are the basic logical elements of quantum information processing (QIP) that may represent the future of computer technology. Since they process problems in a quantum-mechanical manner, such quantum computers might one day solve complex problems much more quickly than currently possible, so the hope of researchers.

link.

Australian Scientists Propose Quantum Computer Chip Architecture

Australian scientists have designed a 3D silicon chip architecture based on single atom quantum bits, which is compatible with atomic-scale fabrication techniques - providing a blueprint to build a large-scale quantum computer.

Scientists and engineers from the Australian Research Council Centre of Excellence for Quantum Computation and Communication Technology (CQC2T), headquartered at the University of New South Wales (UNSW), are leading the world in the race to develop a scalable quantum computer in silicon - a material well-understood and favoured by the trillion-dollar computing and microelectronics industry.

link.

Scalable Quantum Computer Architecture Proposed

Within the last several years, considerable progress has been made in developing a quantum computer, which holds the promise of solving problems a lot more efficiently than a classical computer. Physicists are now able to realize the basic building blocks, the quantum bits (qubits) in a laboratory, control them and use them for simple computations. For practical application, a particular class of quantum computers, the so-called adiabatic quantum computer, has recently generated a lot of interest among researchers and industry. It is designed to solve real-world optimization problems conventional computers are not able to tackle. All current approaches for adiabatic quantum computation face the same challenge: The problem is encoded in the interaction between qubits; to encode a generic problem, an all-to-all connectivity is necessary, but the locality of the physical quantum bits limits the available interactions. "The programming language of these systems is the individual interaction between each physical qubit. The possible input is determined by the hardware. This means that all these approaches face a fundamental challenge when trying to build a fully programmable quantum computer," explains Wolfgang Lechner from the Institute for Quantum Optics and Quantum Information (IQOQI) at the Austrian Academy of Sciences in Innsbruck.

link.

Beyond Exascale Supercomputers: IARPA Launches Cryogenic Computer Complexity Program

American intelligence agencies announced plans Friday to develop and build a new superconducting supercomputer, one which would increase current computing capacity while simultaneously reducing the energy consumption and physical footprint of the machines.

The Intelligence Advanced Research Projects Activity, a branch of the U.S. intelligence community, said in a press release that the agency has embarked on a multi-year research effort called the Cryogenic Computer Complexity program, or C3.

Current supercomputing utilizes technology that relies on tens of megawatts and requires large amounts of physical space to house the infrastructure and power and cool the components.

C3 hopes to use recent breakthroughs in supercomputing technologies — "new families of superconducting logic without static power dissipation and new ideas for energy efficient cryogenic memory" — to construct a superconducting supercomputer with "a simplified cooling infrastructure and a greatly reduced footprint."

"The power, space, and cooling requirements for current supercomputers based on complementary metal oxide semiconductor (CMOS) technology are becoming unmanageable," said Marc Manheimer, C3 program manager at IARPA.

"Computers based on superconducting logic integrated with new kinds of cryogenic memory will allow expansion of current computing facilities while staying within space and energy budgets, and may enable supercomputer development beyond the exascale," Manheimer said.

link.

cryogenics and hpc?  this will only end well.

The Limits of the Limits for Processors

Limits on fundamental limits to computation

Author:

Markov

Abstract:

An indispensable part of our personal and working lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the past fifty years. Such Moore scaling now requires ever-increasing efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and increase our understanding of integrated-circuit scaling, here I review fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, I recapitulate how some limits were circumvented, and compare loose and tight limits. Engineering difficulties encountered by emerging technologies may indicate yet unknown limits.

pop sci write up of the same.

Tip Toeing to the Robopocaylpse With IBM

A million spiking-neuron integrated circuit with a scalable communication network and interface

Authors:

Merolla et al

Abstract:

Inspired by the brain’s structure, we have developed an efficient, scalable, and flexible non–von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.

pop sci write up.

Memristers Finally Here? HP to Ship in 2016?

A replacement for the ordinary transistor may make it to market by the end of this decade, an event that will herald a radical redesign of traditional computer architectures. The memristor, the subject of much study over the last six years, could become the basic building block for an array of new devices—from the sensors and memory chips being built into the "Internet of Things" (connected, sensor-embedded devices) to the giant computers used for big data applications by scientists, engineers and Wall Street.

[...]

The industry has several goals in making the shift. Memristors can vastly improve energy efficiency of electronic components, and are better able to cope with the floods of data expected from the Internet of Things, which monitor or control equipment or systems in factories, office buildings or homes. Essential to their development is a continuation of the exponential growth in computing power and storage density that has seen prices plunge over the past 40 years. For similar reasons, IBM has just announced it will spend $3 billion to pursue experimental "post-silicon" architectures and chips, predicting a fundamental revamping of existing systems in 10 years.

These changes will produce a fundamental overhaul of computer operating systems to accommodate hardware that no longer differentiates between dynamic memory and long-term storage. Bresniker sees the change as an opportunity to jettison layers of cumbersome operating system code that was previously adopted to accommodate the limitations of older hardware.

HP's current development timetable has memristors going into the earliest stage of production in 2015 and launching as DIMMs (dual in-line memory modules) for computer memory in 2016. The operating system for “The Machine” will go into wider public beta testing in 2017, and the new architecture is intended to be integrated into actual products in 2019. Even if none of this pans out, Bresniker believes the attempt is worth it: "Each of the elements is interesting…[on its own]. Pulling out that copper and dropping in that piece of fiber will be more efficient, even with a traditional computing and memory regime all around it…. We need a replacement memory technology. If it does nothing else than drop in where my DIMMs drop in today, that will be a useful thing."

link.

Hewlett Packard is Attempting to Reinvent Computers' Fundamental Architecture

If Hewlett-Packard (HPQ) founders Bill Hewlett and Dave Packard are spinning in their graves, they may be due for a break. Their namesake company is cooking up some awfully ambitious industrial-strength computing technology that, if and when it’s released, could replace a data center’s worth of equipment with a single refrigerator-size machine.

That’s what they’re calling it at HP Labs: “the Machine.” It’s basically a brand-new type of computer architecture that HP’s engineers say will serve as a replacement for today’s designs, with a new operating system, a different type of memory, and superfast data transfer. The company says it will bring the Machine to market within the next few years or fall on its face trying. “We think we have no choice,” says Martin Fink, the chief technology officer and head of HP Labs, who is expected to unveil HP’s plans at a conference Wednesday.

A decade ago, it wouldn’t seem as outlandish as it now does for a company such as HP, IBM (IBM), or Sun Microsystems to build a new computer architecture from the ground up. The hardware powerhouses, known as systems companies, all made their own chips, networking technology, and custom OS. Then commodity components became more powerful, and better data center software began to make up for deficiencies in the cheaper hardware. Consumer Web companies such as Google, Amazon.com (AMZN), and Yahoo! (YHOO) advanced new data center designs that were quickly adopted by the mainstream, shrinking the market share of the systems companies.

HP Labs, the company’s R&D arm, was once revered throughout Silicon Valley as a steady source of new products that could open up new markets. It’s been far less inspiring in recent years, ginning up a mishmash of mobile software, printing services, and teleconferencing systems that haven’t made it to customers in a meaningful way. Amid budget cuts, a costly, complex new computer system would seem like a stretch.

link.

Stanford Flirts With the Robopocalypse

Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations

Authors:

Benjamin et al

Abstract:

In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elements—axonal arbor, synapse, dendritic tree, and soma—with dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realized all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and 3) we interconnected neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time—for the first time—using 16 Neurocores integrated on a board that consumes three watts.

One Time Use Memory Through Quantum Entanglement

Computer security systems may one day get a boost from quantum physics, as a result of recent research from the National Institute of Standards and Technology (NIST). Computer scientist Yi-Kai Liu has devised away to make a security device that has proved notoriously difficult to build—a "one-shot" memory unit, whose contents can be read only a single time.

The research, which Liu is presenting at this week's Innovations in Theoretical Computer Science conference,* shows in theory how the laws of quantum physics could allow for the construction of such memory devices. One-shot memories would have a wide range of possible applications such as protecting the transfer of large sums of money electronically. A one-shot memory might contain two authorization codes: one that credits the recipient's bank account and one that credits the sender's bank account, in case the transfer is canceled. Crucially, the memory could only be read once, so only one of the codes can be retrieved, and hence, only one of the two actions can be performed—not both.

"When an adversary has physical control of a device—such as a stolen cell phone—software defenses alone aren't enough; we need to use tamper-resistant hardware to provide security," Liu says. "Moreover, to protect critical systems, we don't want to rely too much on complex defenses that might still get hacked. It's better if we can rely on fundamental laws of nature, which are unassailable."

Unfortunately, there is no fundamental solution to the problem of building tamper-resistant chips, at least not using classical physics alone. So scientists have tried involving quantum mechanics as well, because information that is encoded into a quantum system behaves differently from a classical system.

Liu is exploring one approach, which stores data using quantum bits, or "qubits," which use quantum properties such as magnetic spin to represent digital information. Using a technique called "conjugate coding, "two secret messages—such as separate authorization codes—can be encoded into the same string of qubits, so that a user can retrieve either one of the two messages. But as the qubits can only be read once, the user cannot retrieve both.

The risk in this approach stems from a more subtle quantum phenomenon: "entanglement," where two particles can affect each other even when separated by great distances. If an adversary is able to use entanglement, he can retrieve both messages at once, breaking the security of the scheme.

However, Liu has observed that in certain kinds of physical systems, it is very difficult to create and use entanglement, and shows in his paper that this obstacle turns out to be an advantage: Liu presents a mathematical proof that if an adversary is unable to use entanglement in his attack, that adversary will never be able to retrieve both messages from the qubits. Hence, if the right physical systems are used, the conjugate coding method is secure after all.

link.

Broadcom Chairman/CTO: Moore's Law Hits Economic Wall

At a wine bar in San Francisco on Wednesday, Broadcom Chairman and CTO Henry Samueli delivered some sobering news: Moore's Law isn't making chips cheaper anymore.

The famed law of microprocessors predicts that packing more transistors onto a silicon wafer will make processors smaller, faster and cheaper with each generation. The ability to get more chips out of each wafer should cut the cost per transistor with each new generation, according to the logic of the law, which was first proposed by Intel co-founder Gordon Moore in the 1960s.

But keeping Moore's Law going now requires complicated manufacturing techniques that are so expensive they cancel out the cost savings that should come with each new generation, said Samueli, who co-founded the giant communications chip maker in 1991.

"The cost curves are kind of getting flat," Samueli told reporters at an evening Broadcom event at the Tank18 wine bar in San Francisco's trendy South of Market district. Instead of getting more speed, less power consumption and lower cost with each generation, chip makers now have to choose two out of three.

He pointed to new techniques such as High-K Metal Gate and FinFET, which have been used in recent years to achieve new so-called process nodes. The most advanced process node on the market, defined by the size of the features on a chip, is due to reach 14 nanometers next year. At levels like that, chip makers need more than traditional manufacturing techniques to achieve the high density, Samueli said. The more dense chips get, the more expensive it will be to make them, he said.

Process nodes themselves still have room to advance, but they may also be headed for a wall in about 15 years, Samueli said. After another three generations or so, chips will probably reach 5nm, and at that point there will be only 10 atoms from the beginning to the end of each transistor gate, he said. Beyond that, further advances may be impossible.

"You can't build a transistor with one atom," Samueli said. There's no obvious path forward at that point, either. "As of yet, we have not seen a viable replacement for the CMOS transistor as we've known it for the last 50 years."

But the impact of cost increases will come sooner, he said. For some types of processors, chip makers will probably stick with current process nodes. They'll only invest in more dense geometries for chips that have to meet growing performance and power-consumption requirements at any cost, Samueli said. This has already happened in the world of analog chips, where manufacturers still use technology that's five years old or more and innovate instead on design, he said.

While some of the network switch chips Broadcom makes, for example, will demand new process nodes, many processors in consumer devices probably won't, he said. "You don't need to build a Wi-Fi chip in 10nm CMOS. You can do it just fine in 28nm."

Where consumer devices do need newer chip technology to maximize battery life, the ongoing bargain of getting more for less eventually will end, Samueli said. "We've been spoiled by these devices getting cheaper and cheaper and cheaper in every generation. We're just going to have to live with prices leveling off," he said.

link.

Computer Science Seminar at LBNL Tomorrow: Krylov-based Methods for Future Extreme Computing

CS Seminar: Toward Smart-tuned Krylov-based Methods for Future Extreme Computing

Berkeley Lab – Computing Sciences Seminar

Date: Thursday, August 15, 2013

Time: 11:00am - 12:00pm

Location: Bldg. 50F, Room 1647

Speaker: Serge G. Petiton

Maison de la Simulation/CNRS and University Lille 1, Sciences et Technologies

Title: Toward Smart-tuned Krylov-based Methods for Future Extreme Computing

Abstract:

Exascale hypercomputers are expected to have highly hierarchical architectures with nodes composed by lot-of-core processors and accelerators. The different programming levels (from clusters of processors loosely connected to tightly connected lot-of-core processors and/or accelerators) will generate new difficult algorithm issues. New methods should be defined and evaluated with respect to modern state-of-the-art of applied mathematics and scientific methods.

Krylov linear methods such as GMRES and ERAM are now heavily used with success in various domains and industries despite their complexity. Their convergence and speed greatly depends on the hardware used and on the choice of the Krylov subspace size and other parameters which are difficult to determine efficiently in advance. Moreover, hybrid Krylov Methods would allow reducing the communications along all the cores, limiting the reduction only through subsets of these cores. Added to their numerical behaviours and their fault tolerance properties, these methods are interesting candidates for exascale/extreme matrix computing. Avoiding communication strategies may also be developed for each of the instance of these methods, generating complex methods but with high potential efficiencies. These methods have a lot of correlated parameter which may be optimized using auto/smart-tuning strategies to accelerate convergence, minimize storage space, data movements, and energy consumption.

In this talk, we first will present some basic matrix operations utilized on Krylov methods on clusters of accelerators, with respect to a few chosen sparse compressed formats. We will discuss some recent experiments on a cluster of accelerators concerning comparison between orthogonal, incompletely orthogonal and non-orthogonal Krylov Basis computing. Then, we will discuss some results obtained on a cluster of accelerators to compute eigenvalues using the MERAM method with respect to the restarting strategies. We will survey some auto/smarttunning strategies we proposed and evaluated for some of the Krylov method parameters. As a conclusion, we will propose auto-tuning strategies for future hybrid methods on post-petascale computers, on the road to exascale hybrid methods.

Joint wok with: Nahid Emad (U. Versailles), Leroy Drummond (LBNL), France Boillod and Christophe Calvin (CEA), Langshi Chen (CNRS), Maxime Hugu

Performance Analysis Gap: Processor Complexity Keeps Climbing – Developers Are More Naïve Than Ever

Performance Analysis Gap: Processor Complexity Keeps Climbing – Developers Are More Naïve Than Ever

Berkeley Lab – Computing Sciences Seminar

Date: Thursday, August 8, 2013

Time: 10:00am - 11:00am

Location: Bldg. 50F, Room 1647

Speaker: Wucherl Yoo

Computer Science Department

University of Illinois

Abstract:

The performance analysis gap is widening as processor complexity keeps climbing and developers are becoming more naïve than ever. Seemingly suitable programs can run correctly, but may suffer from hidden hardware bottlenecks that can severely hinder performance. Performance Monitoring Unit (PMU) events can provide programmers with unique and powerful insights into performance problems in their programs, but interpreting these events has been a significant challenge. While the conventional performance tuning tools can measure and visualize hardware events, they lack automatic identification of dominant resource bottlenecks and significant manual effort is required from experts to interpret the hardware events. 

ARGH!

IDK if I can make it.  I really ought to, but,,,

Heterogenous Computing Seminar at LBNL

CS Seminar: Introduction to Programming on Heterogeneous Computing Systems
Berkeley Lab – Computing Sciences Seminar
Date:
Monday, April 1, 2013

Time:
10:00am - 11:00am

Location:
Bldg. 50F, Room 1647

Speaker:
Mayank Daga
Snr. Software Engineer
AMD Reseach

Title:
Introduction to Programming on Heterogeneous Computing Systems

Abstract:
We will talk about GPUs in general. What are some of the differences between programming CPUs and GPUs. How do we use OpenCL. Overview of the architecture of latest AMD GPUs/APUs

Host of Seminar:
Weiqun Zhang, CCSE
Lawrence Berkeley National Laboratory

 I don't know if I can make this one, but I am going to try.  If there is a video feed, I'llsee if I am allowed to post it.