Columbia Engineering researchers have, for the first time, harnessed the molecular machinery of living systems to power an integrated circuit from adenosine triphosphate (ATP), the energy currency of life. They achieved this by integrating a conventional solid-state complementary metal-oxide-semiconductor (CMOS) integrated circuit with an artificial lipid bilayer membrane containing ATP-powered ion pumps, opening the door to creating entirely new artificial systems that contain both biological and solid-state components. The study, led by Ken Shepard, Lau Family Professor of Electrical Engineering and professor of biomedical engineering at Columbia Engineering, is published online Dec. 7 in Nature Communications.
China's Tsinghua Unigroup Ltd plans to invest 300 billion yuan ($47 billion) over the next five years in a bid to become the world's third-biggest chipmaker, the chairman of the state-backed technology conglomerate said on Monday.
Chairman Zhao Weiguo also told Reuters in an interview in Beijing that the company controlled by Tsinghua University, which counts President Xi Jinping among its alumni, was in talks with a U.S.-based company involved in the chip industry.
A deal could be finalized as early as the end of this month, he said. He declined to give more details but said buying a majority stake was unlikely as it was too "sensitive" for the U.S. government.
"If you can't be the top-three giant, it will be very hard to develop your business in the chip industry," Zhao said, citing reports that China imported more chips than crude oil every year.
"The next five years is key... There is an enormous market out there."
A million spiking-neuron integrated circuit with a scalable communication network and interface
Authors:
Merolla et al
Abstract:
Inspired by the brain’s structure, we have developed an efficient, scalable, and flexible non–von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.
pop sci write up.
At a wine bar in San Francisco on Wednesday, Broadcom Chairman and CTO Henry Samueli delivered some sobering news: Moore's Law isn't making chips cheaper anymore.
The famed law of microprocessors predicts that packing more transistors onto a silicon wafer will make processors smaller, faster and cheaper with each generation. The ability to get more chips out of each wafer should cut the cost per transistor with each new generation, according to the logic of the law, which was first proposed by Intel co-founder Gordon Moore in the 1960s.
But keeping Moore's Law going now requires complicated manufacturing techniques that are so expensive they cancel out the cost savings that should come with each new generation, said Samueli, who co-founded the giant communications chip maker in 1991.
"The cost curves are kind of getting flat," Samueli told reporters at an evening Broadcom event at the Tank18 wine bar in San Francisco's trendy South of Market district. Instead of getting more speed, less power consumption and lower cost with each generation, chip makers now have to choose two out of three.
He pointed to new techniques such as High-K Metal Gate and FinFET, which have been used in recent years to achieve new so-called process nodes. The most advanced process node on the market, defined by the size of the features on a chip, is due to reach 14 nanometers next year. At levels like that, chip makers need more than traditional manufacturing techniques to achieve the high density, Samueli said. The more dense chips get, the more expensive it will be to make them, he said.
Process nodes themselves still have room to advance, but they may also be headed for a wall in about 15 years, Samueli said. After another three generations or so, chips will probably reach 5nm, and at that point there will be only 10 atoms from the beginning to the end of each transistor gate, he said. Beyond that, further advances may be impossible.
"You can't build a transistor with one atom," Samueli said. There's no obvious path forward at that point, either. "As of yet, we have not seen a viable replacement for the CMOS transistor as we've known it for the last 50 years."
But the impact of cost increases will come sooner, he said. For some types of processors, chip makers will probably stick with current process nodes. They'll only invest in more dense geometries for chips that have to meet growing performance and power-consumption requirements at any cost, Samueli said. This has already happened in the world of analog chips, where manufacturers still use technology that's five years old or more and innovate instead on design, he said.
While some of the network switch chips Broadcom makes, for example, will demand new process nodes, many processors in consumer devices probably won't, he said. "You don't need to build a Wi-Fi chip in 10nm CMOS. You can do it just fine in 28nm."
Where consumer devices do need newer chip technology to maximize battery life, the ongoing bargain of getting more for less eventually will end, Samueli said. "We've been spoiled by these devices getting cheaper and cheaper and cheaper in every generation. We're just going to have to live with prices leveling off," he said.
One of the strangest effects to arise from the quantum nature of the universe is the Casimir force. This pushes two parallel conducting plates together when they are just a few dozen nanometres apart.
At these kinds of scales, the Casimir force can dominate and engineers are well aware of its unwanted effects. One reason why microelectromechanical machines have never reached their original promise is the stiction that Casimir forces can generate.
On the other hand, many engineers hope to exploit the Casimir force. Various theoretical models predict that the force should be repulsive between objects of certain shapes, a phenomenon that could prevent stiction.
But there is a problem: Casimir force experiments are extremely hard to do. One headache is that nobody has perfected the technology to position different objects accurately with a nanometre scale gap. Another is that microscopic objects tend to warp and bend; any corrugations on a flat surface can dramatically change the amount of Casimir force between them and even its direction. That makes experimental results hard to interpret.
Today, Jie Zou at the University of Florida and a few buddies take a big step towards changing this. These guys have carved a single device out of silicon that is capable of measuring the Casimir force between a pair of parallel silicon beams, the first on-chip device capable of doing this.
The device consists of one fixed beam and another moveable one attached to an electromechanical actuator. The team starts by measuring the separation between them using a scanning electron microscope. They then apply a voltage to the actuator, which pushes the movable beam towards the fixed beam.
The beams oscillate at a natural frequency, which Zou and co can easily measure. However, this frequency depends on the forces on the beams. So as the beams move closer together and the Casimir forces changes, so too does the oscillation frequency. This is how Zou and co measure the force.
Of course, there are other forces at play here too, such as residual electrostatic forces. When Zou and co take these into account, their results more or less exactly match theoretical predictions for the Casimir force that beams of this shape should generate.
